Field of the Invention
The present invention relates to an information processing apparatus, and a method for controlling power of an information processing apparatus.
Description of the Related Art
Conventionally, an information processing apparatus is provided with an integrated circuit that can be configured to be set by a consumer or a designer after being manufactured, and performs image processing or the like while reconfiguring a logical configuration for dynamically processing a requested job (configuration). One example of such an integrated circuit is a field-programmable gate array (FPGA). There is a technique that connects a programmable logic device (PLD), which controls the FPGA configuration, and a microcomputer to each other via a control line to ensure that the microcomputer can access this FPGA after completion of the configuration.
According to Japanese Patent Application Laid-Open No. 2003-15777, the PLD notifies the microcomputer of the completion of the FPGA configuration via the control line, which allows the microcomputer to recognize a timing at which the FPGA becomes accessible. This mechanism can contribute to a stable and quick start-up of a configuration apparatus system, and improvement in a system performance thereof.
This technique can be also applied in a case where, for example, the FPGA is connected to a host central processing unit (CPU) via a bus such as a Peripheral Component Interconnect Express (PCIe) bus, and the host CPU recognizes the FPGA as a PCIe device. More specifically, the host CPU can reliably detect the FPGA as the PCIe device by being notified of the completion of the configuration of the FPGA including a PCIe control unit, which corresponds to an end point. The host CPU can search for the PCIe device after this notification.
The information processing apparatus desirably reduces a boot-up time taken after the information processing apparatus is powered on.
There is a method that refrains from configuring an entire logic of the FPGA during a sequence of booting up a system, and postpones the configuring until later processing, because this processing takes a time of approximately several hundred microseconds.
For example, the information processing apparatus can reduce the time taken to boot up the entire system if the configuring of the FPGA is carried out in an idle state after the boot-up processing, or immediately before carrying out the FPGA function.
However, in the system that uses the FPGA while causing the host CPU to recognize the FPGA as the PCIe device, at least the configuration of the PCIe control unit of the FPGA should be completed before the host CPU searches for the PCIe device.
Generally, the host CPU searches for the PCIe device while a Basic Input/Output System (BIOS) or the like is being booted up, whereby the method that configures the entire FPGA after the boot-up as described above does not allow the host CPU to recognize the FPGA as the PCIe device.